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+From 45187e2f9c73ea96e69d1f46f0c24ff31d7f9298 Mon Sep 17 00:00:00 2001
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+From: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
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+Date: Tue, 28 Sep 2021 11:25:25 +0100
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+Subject: [PATCH 2/2] Extend Stage 1 mapping limit
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+
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+As Stage 1 mappings are limited to 512GB, registering FF-A RxTx buffers
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+fails when the physical address of these buffers exceeds 512GB. This
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+fix removes the limitation and allows Stage 1 mapping up to the
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+supported PA range.
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+
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+Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
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+Change-Id: I4cb8d68fc18e0edf4a7ee06ae636849d552d72a9
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+Upstream-Status: Pending [Not submitted to upstream yet]
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+---
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+ inc/hf/arch/mm.h | 7 ++++++-
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+ src/arch/aarch64/mm.c | 38 ++++++++++++++++++++++++++------------
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+ src/arch/fake/mm.c | 9 +++++++--
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+ src/mm.c | 8 +++++++-
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+ 4 files changed, 46 insertions(+), 16 deletions(-)
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+
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+diff --git a/inc/hf/arch/mm.h b/inc/hf/arch/mm.h
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+index ef64dd3..d277369 100644
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+--- a/inc/hf/arch/mm.h
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++++ b/inc/hf/arch/mm.h
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+@@ -162,7 +162,12 @@ uint32_t arch_mm_stage1_attrs_to_mode(uint64_t attrs);
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+ /**
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+ * Initializes the arch specific memory management.
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+ */
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+-bool arch_mm_init(paddr_t table);
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++bool arch_mm_init(void);
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++
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++/**
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++ * Set ptable base address.
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++ */
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++void arch_mm_set_ptable(paddr_t table);
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+
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+ /**
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+ * Return the arch specific mm mode for send/recv pages of given VM ID.
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+diff --git a/src/arch/aarch64/mm.c b/src/arch/aarch64/mm.c
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+index 7256c28..0ee0bb6 100644
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+--- a/src/arch/aarch64/mm.c
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++++ b/src/arch/aarch64/mm.c
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+@@ -141,6 +141,7 @@ struct arch_mm_config {
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+ uintreg_t hcr_el2;
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+ } arch_mm_config;
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+
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++static uint8_t mm_s1_max_level;
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+ static uint8_t mm_s2_max_level;
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+ static uint8_t mm_s2_root_table_count;
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+
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+@@ -676,12 +677,7 @@ uint32_t arch_mm_stage2_attrs_to_mode(uint64_t attrs)
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+
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+ uint8_t arch_mm_stage1_max_level(void)
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+ {
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+- /*
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+- * For stage 1 we hard-code this to 2 for now so that we can
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+- * save one page table level at the expense of limiting the
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+- * physical memory to 512GB.
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+- */
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+- return 2;
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++ return mm_s1_max_level;
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+ }
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+
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+ uint8_t arch_mm_stage2_max_level(void)
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+@@ -735,10 +731,16 @@ uint64_t arch_mm_combine_table_entry_attrs(uint64_t table_attrs,
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+ return block_attrs;
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+ }
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+
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++void
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++arch_mm_set_ptable(paddr_t table)
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++{
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++ arch_mm_config.ttbr0_el2 = pa_addr(table);
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++}
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++
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+ /**
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+ * This is called early in initialization without MMU or caches enabled.
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+ */
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+-bool arch_mm_init(paddr_t table)
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++bool arch_mm_init(void)
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+ {
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+ static const int pa_bits_table[16] = {32, 36, 40, 42, 44, 48};
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+ uint64_t features = read_msr(id_aa64mmfr0_el1);
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+@@ -784,6 +786,13 @@ bool arch_mm_init(paddr_t table)
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+ mm_s2_max_level = 1;
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+ }
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+
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++ if (pa_bits >= 40) {
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++ mm_s1_max_level = 3;
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++ } else {
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++ /* Setting to 2 covers physical memory upto 512GB */
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++ mm_s1_max_level = 2;
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++ }
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++
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+ /*
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+ * Since the shallowest possible tree is used, the maximum number of
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+ * concatenated tables must be used. This means if no more than 4 bits
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+@@ -800,6 +809,10 @@ bool arch_mm_init(paddr_t table)
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+ "Stage 2 has %d page table levels with %d pages at the root.\n",
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+ mm_s2_max_level + 1, mm_s2_root_table_count);
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+
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++ dlog_info("Stage 1 has %d page table levels with %d pages at the "
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++ "root.\n", mm_s1_max_level + 1,
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++ arch_mm_stage1_root_table_count());
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++
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+ /*
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+ * If the PE implements S-EL2 then VTCR_EL2.NSA/NSW bits are significant
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+ * in secure state. In non-secure state, NSA/NSW behave as if set to
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+@@ -818,8 +831,6 @@ bool arch_mm_init(paddr_t table)
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+ }
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+
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+ arch_mm_config = (struct arch_mm_config){
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+- .ttbr0_el2 = pa_addr(table),
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+-
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+ .vtcr_el2 =
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+ (1U << 31) | /* RES1. */
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+ (nsa_nsw << 29) | /* NSA/NSW. */
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+@@ -879,14 +890,16 @@ bool arch_mm_init(paddr_t table)
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+ << 24) | /* IRGN1, normal mem, WB RA WA Cacheable. */
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+ (1UL << 23) | /* EPD1 - Disable TTBR1_EL2 translation */
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+ (0UL << 22) | /* TTBR0_EL2.ASID defines ASID */
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+- (25UL << 16) | /* T1SZ, input address is 2^39 bytes. */
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++ ((64 - pa_bits) << 16) | /* T1SZ, input address is *
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++ 2^pa_bits bytes. */
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+ (0UL << 14) | /* TG0, granule size, 4KB. */
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+ (3UL << 12) | /* SH0, inner shareable. */
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+ (1UL
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+ << 10) | /* ORGN0, normal mem, WB RA WA Cacheable. */
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+ (1UL
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+ << 8) | /* IRGN0, normal mem, WB RA WA Cacheable. */
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+- (25UL << 0) | /* T0SZ, input address is 2^39 bytes. */
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++ ((64 - pa_bits) << 0) | /* T0SZ, input address is *
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++ 2^pa_bits bytes. */
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+ 0;
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+ } else {
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+ arch_mm_config.tcr_el2 =
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+@@ -896,7 +909,8 @@ bool arch_mm_init(paddr_t table)
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+ (3 << 12) | /* SH0, inner shareable. */
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+ (1 << 10) | /* ORGN0, normal mem, WB RA WA Cacheable. */
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+ (1 << 8) | /* IRGN0, normal mem, WB RA WA Cacheable. */
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+- (25 << 0) | /* T0SZ, input address is 2^39 bytes. */
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++ ((64 - pa_bits) << 0) | /* T0SZ, input address is *
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++ 2^pa_bits bytes. */
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+ 0;
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+ }
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+ return true;
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+diff --git a/src/arch/fake/mm.c b/src/arch/fake/mm.c
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+index e06a8b7..8ac63fa 100644
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+--- a/src/arch/fake/mm.c
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++++ b/src/arch/fake/mm.c
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+@@ -161,13 +161,18 @@ uint32_t arch_mm_stage1_attrs_to_mode(uint64_t attrs)
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+ return attrs >> PTE_ATTR_MODE_SHIFT;
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+ }
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+
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+-bool arch_mm_init(paddr_t table)
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++bool arch_mm_init(void)
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+ {
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+ /* No initialization required. */
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+- (void)table;
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+ return true;
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+ }
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+
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++void arch_mm_set_ptable(paddr_t table)
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++{
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++ /* No initialization required. */
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++ (void)table;
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++}
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++
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+ uint32_t arch_mm_extra_attributes_from_vm(ffa_vm_id_t id)
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+ {
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+ (void)id;
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+diff --git a/src/mm.c b/src/mm.c
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+index c57e24e..aa0c512 100644
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+--- a/src/mm.c
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++++ b/src/mm.c
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+@@ -1114,6 +1114,10 @@ bool mm_init(struct mpool *ppool)
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+ dlog_info("data: %#x - %#x\n", pa_addr(layout_data_begin()),
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+ pa_addr(layout_data_end()));
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+
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++ if (!arch_mm_init()) {
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++ return false;
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++ }
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++
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+ /* ASID 0 is reserved for use by the hypervisor. */
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+ if (!mm_ptable_init(&ptable, 0, MM_FLAG_STAGE1, ppool)) {
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+ dlog_error("Unable to allocate memory for page table.\n");
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+@@ -1133,5 +1137,7 @@ bool mm_init(struct mpool *ppool)
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+ mm_identity_map(stage1_locked, layout_data_begin(), layout_data_end(),
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+ MM_MODE_R | MM_MODE_W, ppool);
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+
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+- return arch_mm_init(ptable.root);
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++ arch_mm_set_ptable(ptable.root);
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++
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++ return true;
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+ }
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+--
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+2.30.2
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+
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Arunachalam Ganapathy