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@@ -0,0 +1,31 @@
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+From a8aeaafd6c26d6bc3066164d12aabc5cb754fe1c Mon Sep 17 00:00:00 2001
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+From: Ali Can Ozaslan <ali.oezaslan@arm.com>
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+Date: Wed, 15 May 2024 12:12:15 +0000
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+Subject: [PATCH] CC312: alignment of cc312 differences between fvp and mps3
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+ corstone1000 platforms
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+
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+Configures CC312 mps3 model same as predefined cc312 FVP
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+configuration while keeping debug ports closed.
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+
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+Signed-off-by: Ali Can Ozaslan <ali.oezaslan@arm.com>
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+
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+Upstream-Status: Inappropriate [Requires an aligment cc3xx with mps3 hw and fvp sw models]
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+
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+---
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+ lib/ext/cryptocell-312-runtime/host/src/cc3x_lib/cc_lib.c | 3 +++
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+ 1 file changed, 3 insertions(+)
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+
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+diff --git a/lib/ext/cryptocell-312-runtime/host/src/cc3x_lib/cc_lib.c b/lib/ext/cryptocell-312-runtime/host/src/cc3x_lib/cc_lib.c
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+index 31e4332be..4d7e6fa61 100644
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+--- a/lib/ext/cryptocell-312-runtime/host/src/cc3x_lib/cc_lib.c
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++++ b/lib/ext/cryptocell-312-runtime/host/src/cc3x_lib/cc_lib.c
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+@@ -207,6 +207,9 @@ CClibRetCode_t CC_LibInit(CCRndContext_t *rndContext_ptr, CCRndWorkBuff_t *rndW
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+ goto InitErr2;
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+ }
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+
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++ /* configuring secure debug to align cc312 with corstone 1000 */
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++ CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF,HOST_DCU_EN0), 0xffffe7fc);
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++
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+ /* turn off the DFA since Cerberus doen't support it */
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+ reg = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_AO_LOCK_BITS));
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+ CC_REG_FLD_SET(0, HOST_AO_LOCK_BITS, HOST_FORCE_DFA_ENABLE, reg, 0x0);
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