arm-bsp/trusted-firmware-a: Upgrade Corstone1000 to TF-A v2.10

Upgrades trusted-firmware-a and align with changes in v2.10 for Corstone-1000.

Signed-off-by: Emekcan Aras <emekcan.aras@arm.com>
Signed-off-by: Delane Brandy <delane.brandy@arm.com>
Signed-off-by: Jon Mason <jon.mason@arm.com>

meta-arm-bsp/conf/machine/include/corstone1000.inc

@@ -7,7 +7,7 @@ PREFERRED_VERSION_trusted-firmware-m ?= "1.8.%"
 
 # TF-A
 TFA_PLATFORM = "corstone1000"
-PREFERRED_VERSION_trusted-firmware-a ?= "2.9.%"
+PREFERRED_VERSION_trusted-firmware-a ?= "2.10.%"
 PREFERRED_VERSION_tf-a-tests ?= "2.8.%"
 
 TFA_BL2_BINARY = "bl2-corstone1000.bin"

meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0002-feat-corstone1000-bl2-loads-fip-based-on-metadata.patch

@@ -1,162 +0,0 @@
-From fa7ab9b40babee29d2aadb267dfce7a96f8989d4 Mon Sep 17 00:00:00 2001
-From: Mohamed Omar Asaker <mohamed.omarasaker@arm.com>
-Date: Mon, 9 Jan 2023 13:59:06 +0000
-Subject: [PATCH] feat(corstone1000): bl2 loads fip based on metadata
-
-Previously bl2 was reading the boot_index directly with a hard coded
-address and then set the fip image spec with fip offsets base based on
-the boot_index value.
-This commit removes this logic and rely on PSA_FWU_SUPPORT
-which reads the fip partition based on the active firmware bank written in
-metadata.
-
-Note: fip partition contains signature area at the begining. Hence, the fip
-image starts at fip partition + fip signature area size.
-
-Upstream-Status: Pending
-Signed-off-by: Mohamed Omar Asaker <mohamed.omarasaker@arm.com>
----
- bl2/bl2_main.c                                |  4 +++
- .../corstone1000/common/corstone1000_plat.c   | 32 ++++++-------------
- .../common/include/platform_def.h             | 12 +++----
- tools/cert_create/Makefile                    |  4 +--
- tools/fiptool/Makefile                        |  4 +--
- 5 files changed, 24 insertions(+), 32 deletions(-)
-
-diff --git a/bl2/bl2_main.c b/bl2/bl2_main.c
-index ce83692e0ebc..1a9febc007b2 100644
---- a/bl2/bl2_main.c
-+++ b/bl2/bl2_main.c
-@@ -87,6 +87,10 @@ void bl2_main(void)
- 	/* Perform remaining generic architectural setup in S-EL1 */
- 	bl2_arch_setup();
- 
-+#if ARM_GPT_SUPPORT
-+	partition_init(GPT_IMAGE_ID);
-+#endif
-+
- #if PSA_FWU_SUPPORT
- 	fwu_init();
- #endif /* PSA_FWU_SUPPORT */
-diff --git a/plat/arm/board/corstone1000/common/corstone1000_plat.c b/plat/arm/board/corstone1000/common/corstone1000_plat.c
-index 0235f8b8474c..7f9708a82489 100644
---- a/plat/arm/board/corstone1000/common/corstone1000_plat.c
-+++ b/plat/arm/board/corstone1000/common/corstone1000_plat.c
-@@ -33,36 +33,17 @@ const mmap_region_t plat_arm_mmap[] = {
- static void set_fip_image_source(void)
- {
- 	const struct plat_io_policy *policy;
--	/*
--	 * metadata for firmware update is written at 0x0000 offset of the flash.
--	 * PLAT_ARM_BOOT_BANK_FLAG contains the boot bank that TF-M is booted.
--	 * As per firmware update spec, at a given point of time, only one bank
--	 * is active. This means, TF-A should boot from the same bank as TF-M.
--	 */
--	volatile uint32_t *boot_bank_flag = (uint32_t *)(PLAT_ARM_BOOT_BANK_FLAG);
--
--	if (*boot_bank_flag > 1) {
--		VERBOSE("Boot_bank is set higher than possible values");
--	}
--
--	VERBOSE("Boot bank flag = %u.\n\r", *boot_bank_flag);
- 
- 	policy = FCONF_GET_PROPERTY(arm, io_policies, FIP_IMAGE_ID);
- 
- 	assert(policy != NULL);
- 	assert(policy->image_spec != 0UL);
- 
-+	/* FIP Partition contains Signature area at the begining which TF-A doesn't expect */
- 	io_block_spec_t *spec = (io_block_spec_t *)policy->image_spec;
-+	spec->offset += FIP_SIGNATURE_AREA_SIZE;
-+	spec->length -= FIP_SIGNATURE_AREA_SIZE;
- 
--	if ((*boot_bank_flag) == 0) {
--		VERBOSE("Booting from bank 0: fip offset = 0x%lx\n\r",
--						PLAT_ARM_FIP_BASE_BANK0);
--		spec->offset = PLAT_ARM_FIP_BASE_BANK0;
--	} else {
--		VERBOSE("Booting from bank 1: fip offset = 0x%lx\n\r",
--						PLAT_ARM_FIP_BASE_BANK1);
--		spec->offset = PLAT_ARM_FIP_BASE_BANK1;
--	}
- }
- 
- void bl2_platform_setup(void)
-@@ -75,6 +56,13 @@ void bl2_platform_setup(void)
- 	set_fip_image_source();
- }
- 
-+void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
-+			       u_register_t arg2, u_register_t arg3)
-+{
-+	arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
-+	NOTICE("CS1k: early at bl2_platform_setup\n");
-+}
-+
- /* corstone1000 only has one always-on power domain and there
-  * is no power control present
-  */
-diff --git a/plat/arm/board/corstone1000/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h
-index 584d485f3ea7..0bfab05a482b 100644
---- a/plat/arm/board/corstone1000/common/include/platform_def.h
-+++ b/plat/arm/board/corstone1000/common/include/platform_def.h
-@@ -173,16 +173,16 @@
- 
- /* NOR Flash */
- 
--#define PLAT_ARM_BOOT_BANK_FLAG		UL(0x08002000)
--#define PLAT_ARM_FIP_BASE_BANK0		UL(0x081EF000)
--#define PLAT_ARM_FIP_BASE_BANK1		UL(0x0916F000)
--#define PLAT_ARM_FIP_MAX_SIZE		UL(0x1ff000)  /* 1.996 MB */
--
- #define PLAT_ARM_NVM_BASE		V2M_FLASH0_BASE
- #define PLAT_ARM_NVM_SIZE		(SZ_32M)  /* 32 MB */
-+#define PLAT_ARM_FIP_MAX_SIZE		UL(0x1ff000)  /* 1.996 MB */
- 
--#define PLAT_ARM_FLASH_IMAGE_BASE	PLAT_ARM_FIP_BASE_BANK0
-+#define PLAT_ARM_FLASH_IMAGE_BASE	UL(0x08000000)
- #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE	PLAT_ARM_FIP_MAX_SIZE
-+#define PLAT_ARM_FIP_OFFSET_IN_GPT	(0x86000)
-+
-+/* FIP Information */
-+#define FIP_SIGNATURE_AREA_SIZE         (0x1000)      /* 4 KB */
- 
- /*
-  * Some data must be aligned on the biggest cache line size in the platform.
-diff --git a/tools/cert_create/Makefile b/tools/cert_create/Makefile
-index 042e844626bd..45b76a022f91 100644
---- a/tools/cert_create/Makefile
-+++ b/tools/cert_create/Makefile
-@@ -78,8 +78,8 @@ INC_DIR += -I ./include -I ${PLAT_INCLUDE} -I ${OPENSSL_DIR}/include
- # directory. However, for a local build of OpenSSL, the built binaries are
- # located under the main project directory (i.e.: ${OPENSSL_DIR}, not
- # ${OPENSSL_DIR}/lib/).
--LIB_DIR := -L ${OPENSSL_DIR}/lib -L ${OPENSSL_DIR}
--LIB := -lssl -lcrypto
-+LIB_DIR := -L ${OPENSSL_DIR}/lib -L ${OPENSSL_DIR} ${BUILD_LDFLAGS} ${BUILD_LDFLAGS} ${BUILD_LDFLAGS} ${BUILD_LDFLAGS} ${BUILD_LDFLAGS} ${BUILD_LDFLAGS}
-+LIB := -lssl -lcrypto ${BUILD_LDFLAGS} ${BUILD_LDFLAGS} ${BUILD_LDFLAGS} ${BUILD_LDFLAGS} ${BUILD_LDFLAGS} ${BUILD_LDFLAGS}
- 
- HOSTCC ?= gcc
- 
-diff --git a/tools/fiptool/Makefile b/tools/fiptool/Makefile
-index 2ebee33931ba..dcfd314bee89 100644
---- a/tools/fiptool/Makefile
-+++ b/tools/fiptool/Makefile
-@@ -39,7 +39,7 @@ HOSTCCFLAGS += -DUSING_OPENSSL3=$(USING_OPENSSL3)
- # directory. However, for a local build of OpenSSL, the built binaries are
- # located under the main project directory (i.e.: ${OPENSSL_DIR}, not
- # ${OPENSSL_DIR}/lib/).
--LDLIBS := -L${OPENSSL_DIR}/lib -L${OPENSSL_DIR} -lcrypto
-+LDLIBS := -L${OPENSSL_DIR}/lib -L${OPENSSL_DIR} -lcrypto ${BUILD_LDFLAGS} ${BUILD_LDFLAGS} ${BUILD_LDFLAGS} ${BUILD_LDFLAGS} ${BUILD_LDFLAGS} ${BUILD_LDFLAGS}
- 
- ifeq (${V},0)
-   Q := @
-@@ -47,7 +47,7 @@ else
-   Q :=
- endif
- 
--INCLUDE_PATHS := -I../../include/tools_share  -I${OPENSSL_DIR}/include
-+INCLUDE_PATHS := -I../../include/tools_share  -I${OPENSSL_DIR}/include ${BUILD_CFLAGS} ${BUILD_CFLAGS} ${BUILD_CFLAGS} ${BUILD_CFLAGS} ${BUILD_CFLAGS} ${BUILD_CFLAGS}
- 
- HOSTCC ?= gcc
- 

meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0003-fix-corstone1000-pass-spsr-value-explicitly.patch

@@ -0,0 +1,32 @@
+From d70a07562d3b0a7b4441922fd3ce136565927d04 Mon Sep 17 00:00:00 2001
+From: Emekcan Aras <Emekcan.Aras@arm.com>
+Date: Wed, 21 Feb 2024 07:57:36 +0000
+Subject: [PATCH] fix(corstone1000): pass spsr value explicitly
+
+Passes spsr value for BL32 (OPTEE) explicitly between different boot
+stages.
+
+Upstream-Status: Pending
+Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
+---
+ .../corstone1000/common/corstone1000_bl2_mem_params_desc.c     | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c b/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
+index fe521a9fa..2cc096f38 100644
+--- a/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
++++ b/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
+@@ -72,7 +72,8 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
+ 		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ 			VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
+ 		.ep_info.pc = BL33_BASE,
+-
++		.ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
++				       DISABLE_ALL_EXCEPTIONS),
+ 		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ 			VERSION_2, image_info_t, 0),
+ 		.image_info.image_base = BL33_BASE,
+-- 
+2.25.1
+
+

meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0004-fix-corstone1000-add-cpuhelper-to-makefile.patch

@@ -1,28 +0,0 @@
-From 33078d8ef143e8c79f06399de46dd26e1d53a220 Mon Sep 17 00:00:00 2001
-From: Gauri Sahnan <Gauri.Sahnan@arm.com>
-Date: Tue, 8 Aug 2023 17:16:51 +0100
-Subject: fix(corstone1000): add cpuhelpers to makefile
-
-Adds cpu_helpers.S to the Makefile to align with the changes in new
-trusted-firmware-a version.
-
-Signed-off-by: Gauri Sahnan <Gauri.Sahnan@arm.com>
-Upstream-Status: Pending [Not submitted to upstream yet]
----
- plat/arm/board/corstone1000/platform.mk | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/plat/arm/board/corstone1000/platform.mk b/plat/arm/board/corstone1000/platform.mk
-index 3edffe087..079e9d6c1 100644
---- a/plat/arm/board/corstone1000/platform.mk
-+++ b/plat/arm/board/corstone1000/platform.mk
-@@ -43,6 +43,7 @@ BL2_SOURCES		+=	plat/arm/board/corstone1000/common/corstone1000_security.c		\
- 				plat/arm/board/corstone1000/common/corstone1000_err.c		\
- 				plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c	\
- 				lib/utils/mem_region.c					\
-+				lib/cpus/aarch64/cpu_helpers.S \
- 				plat/arm/board/corstone1000/common/corstone1000_helpers.S		\
- 				plat/arm/board/corstone1000/common/corstone1000_plat.c		\
- 				plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c \
--- 
-2.25.1

meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0004-fix-spmd-remove-EL3-interrupt-registration.patch

@@ -0,0 +1,54 @@
+From 684b8f88238f522b52eb102485762e02e6b1671a Mon Sep 17 00:00:00 2001
+From: Emekcan Aras <Emekcan.Aras@arm.com>
+Date: Fri, 23 Feb 2024 13:17:59 +0000
+Subject: [PATCH] fix(spmd): remove EL3 interrupt registration
+
+This configuration should not be done for corstone1000 and similar
+platforms. GICv2 systems only support EL3 interrupts and can have SEL1 component
+as SPMC.
+
+Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
+Upstream-Status: Inappropriate [Discussions of fixing this in a better way is ongoing in upstream]
+---
+ services/std_svc/spmd/spmd_main.c | 24 ------------------------
+ 1 file changed, 24 deletions(-)
+
+diff --git a/services/std_svc/spmd/spmd_main.c b/services/std_svc/spmd/spmd_main.c
+index 066571e9b..313f05bf3 100644
+--- a/services/std_svc/spmd/spmd_main.c
++++ b/services/std_svc/spmd/spmd_main.c
+@@ -580,30 +580,6 @@ static int spmd_spmc_init(void *pm_addr)
+ 		panic();
+ 	}
+ 
+-	/*
+-	 * Permit configurations where the SPM resides at S-EL1/2 and upon a
+-	 * Group0 interrupt triggering while the normal world runs, the
+-	 * interrupt is routed either through the EHF or directly to the SPMD:
+-	 *
+-	 * EL3_EXCEPTION_HANDLING=0: the Group0 interrupt is routed to the SPMD
+-	 *                   for handling by spmd_group0_interrupt_handler_nwd.
+-	 *
+-	 * EL3_EXCEPTION_HANDLING=1: the Group0 interrupt is routed to the EHF.
+-	 *
+-	 */
+-#if (EL3_EXCEPTION_HANDLING == 0)
+-	/*
+-	 * Register an interrupt handler routing Group0 interrupts to SPMD
+-	 * while the NWd is running.
+-	 */
+-	rc = register_interrupt_type_handler(INTR_TYPE_EL3,
+-					     spmd_group0_interrupt_handler_nwd,
+-					     flags);
+-	if (rc != 0) {
+-		panic();
+-	}
+-#endif
+-
+ 	return 0;
+ }
+ 
+-- 
+2.25.1
+
+

meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc

@@ -5,9 +5,9 @@ COMPATIBLE_MACHINE = "(corstone1000)"
 FILESEXTRAPATHS:prepend := "${THISDIR}/files/corstone1000:"
 SRC_URI:append = " \
 	file://0001-Fix-FF-A-version-in-SPMC-manifest.patch \
-	file://0002-feat-corstone1000-bl2-loads-fip-based-on-metadata.patch \
-	file://0003-psci-SMCCC_ARCH_FEATURES-discovery-through-PSCI_FEATURES.patch \
-	file://0004-fix-corstone1000-add-cpuhelper-to-makefile.patch \
+	file://0002-psci-SMCCC_ARCH_FEATURES-discovery-through-PSCI_FEATURES.patch \
+	file://0003-fix-corstone1000-pass-spsr-value-explicitly.patch \
+	file://0004-fix-spmd-remove-EL3-interrupt-registration.patch \
        "
 
 TFA_DEBUG = "1"
@@ -51,4 +51,5 @@ EXTRA_OEMAKE:append = " \
                         ERRATA_A35_855472=1 \
                         ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
                         BL32=${RECIPE_SYSROOT}/${nonarch_base_libdir}/firmware/tee-pager_v2.bin \
+                        FVP_USE_GIC_DRIVER=FVP_GICV2 \
                         "