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+From 9366c328518766d896155388726055624716c0af Mon Sep 17 00:00:00 2001
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+From: Wilco Dijkstra <wilco.dijkstra@arm.com>
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+Date: Tue, 10 Dec 2024 14:22:48 +0000
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+Subject: [PATCH] arm: Fix LDRD register overlap [PR117675]
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+
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+The register indexed variants of LDRD have complex register overlap constraints
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+which makes them hard to use without using output_move_double (which can't be
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+used for atomics as it doesn't guarantee to emit atomic LDRD/STRD when required).
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+Add a new predicate and constraint for plain LDRD/STRD with base or base+imm.
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+This blocks register indexing and fixes PR117675.
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+
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+gcc:
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+ PR target/117675
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+ * config/arm/arm.cc (arm_ldrd_legitimate_address): New function.
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+ * config/arm/arm-protos.h (arm_ldrd_legitimate_address): New prototype.
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+ * config/arm/constraints.md: Add new Uo constraint.
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+ * config/arm/predicates.md (arm_ldrd_memory_operand): Add new predicate.
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+ * config/arm/sync.md (arm_atomic_loaddi2_ldrd): Use
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+ arm_ldrd_memory_operand and Uo.
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+
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+gcc/testsuite:
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+ PR target/117675
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+ * gcc.target/arm/pr117675.c: Add new test.
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+
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+(cherry picked from commit 21fbfae2e55e1a153820acc6fbd922e66f67e65b)
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+
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+Upstream-Status: Backport [https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117675]
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+---
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+ gcc/config/arm/arm-protos.h | 1 +
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+ gcc/config/arm/arm.cc | 24 ++++++++++++++++++++++++
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+ gcc/config/arm/constraints.md | 8 +++++++-
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+ gcc/config/arm/predicates.md | 4 ++++
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+ gcc/config/arm/sync.md | 2 +-
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+ gcc/testsuite/gcc.target/arm/pr117675.c | 17 +++++++++++++++++
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+ 6 files changed, 54 insertions(+), 2 deletions(-)
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+ create mode 100644 gcc/testsuite/gcc.target/arm/pr117675.c
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+
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+--- a/gcc/config/arm/arm-protos.h
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++++ b/gcc/config/arm/arm-protos.h
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+@@ -202,6 +202,7 @@ extern rtx arm_load_tp (rtx);
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+ extern bool arm_coproc_builtin_available (enum unspecv);
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+ extern bool arm_coproc_ldc_stc_legitimate_address (rtx);
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+ extern rtx arm_stack_protect_tls_canary_mem (bool);
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++extern bool arm_ldrd_legitimate_address (rtx);
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+
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+
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+ #if defined TREE_CODE
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+--- a/gcc/config/arm/arm.cc
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++++ b/gcc/config/arm/arm.cc
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+@@ -34523,6 +34523,30 @@ arm_coproc_ldc_stc_legitimate_address (r
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+ return false;
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+ }
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+
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++/* Return true if OP is a valid memory operand for LDRD/STRD without any
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++ register overlap restrictions. Allow [base] and [base, imm] for now. */
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++bool
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++arm_ldrd_legitimate_address (rtx op)
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++{
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++ if (!MEM_P (op))
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++ return false;
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++
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++ op = XEXP (op, 0);
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++ if (REG_P (op))
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++ return true;
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++
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++ if (GET_CODE (op) != PLUS)
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++ return false;
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++ if (!REG_P (XEXP (op, 0)) || !CONST_INT_P (XEXP (op, 1)))
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++ return false;
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++
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++ HOST_WIDE_INT val = INTVAL (XEXP (op, 1));
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++
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++ if (TARGET_ARM)
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++ return IN_RANGE (val, -255, 255);
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++ return IN_RANGE (val, -1020, 1020) && (val & 3) == 0;
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++}
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++
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+ /* Return the diagnostic message string if conversion from FROMTYPE to
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+ TOTYPE is not allowed, NULL otherwise. */
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+
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+--- a/gcc/config/arm/constraints.md
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++++ b/gcc/config/arm/constraints.md
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+@@ -39,7 +39,7 @@
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+ ;; in all states: Pg
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+
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+ ;; The following memory constraints have been used:
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+-;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us, Up, Uf, Ux, Ul
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++;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us, Uo, Up, Uf, Ux, Ul, Uz
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+ ;; in ARM state: Uq
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+ ;; in Thumb state: Uu, Uw
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+ ;; in all states: Q
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+@@ -585,6 +585,12 @@
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+ (and (match_code "mem")
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+ (match_test "arm_coproc_ldc_stc_legitimate_address (op)")))
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+
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++(define_memory_constraint "Uo"
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++ "@internal
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++ A memory operand for Arm/Thumb-2 LDRD/STRD"
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++ (and (match_code "mem")
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++ (match_test "arm_ldrd_legitimate_address (op)")))
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++
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+ ;; We used to have constraint letters for S and R in ARM state, but
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+ ;; all uses of these now appear to have been removed.
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+
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+--- a/gcc/config/arm/predicates.md
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++++ b/gcc/config/arm/predicates.md
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+@@ -849,6 +849,10 @@
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+ (and (match_operand 0 "memory_operand")
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+ (match_code "reg" "0")))
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+
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++;; True if the operand is memory reference suitable for a ldrd/strd.
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++(define_predicate "arm_ldrd_memory_operand"
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++ (match_test "arm_ldrd_legitimate_address (op)"))
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++
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+ ;; Predicates for parallel expanders based on mode.
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+ (define_special_predicate "vect_par_constant_high"
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+ (match_code "parallel")
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+--- a/gcc/config/arm/sync.md
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++++ b/gcc/config/arm/sync.md
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+@@ -161,7 +161,7 @@
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+ (define_insn "arm_atomic_loaddi2_ldrd"
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+ [(set (match_operand:DI 0 "register_operand" "=r")
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+ (unspec_volatile:DI
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+- [(match_operand:DI 1 "memory_operand" "m")]
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++ [(match_operand:DI 1 "arm_ldrd_memory_operand" "Uo")]
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+ VUNSPEC_LDRD_ATOMIC))]
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+ "ARM_DOUBLEWORD_ALIGN && TARGET_HAVE_LPAE"
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+ "ldrd\t%0, %H0, %1"
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+--- /dev/null
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++++ b/gcc/testsuite/gcc.target/arm/pr117675.c
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+@@ -0,0 +1,17 @@
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++/* { dg-do compile } */
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++/* { dg-options "-O2 -marm" } */
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++/* { dg-require-effective-target arm_arch_v7ve_neon_ok } */
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++/* { dg-add-options arm_arch_v7ve_neon } */
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++/* { dg-final { check-function-bodies "**" "" "" } } */
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++
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++/*
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++** f1:
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++** add r0, r0, r1
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++** ldrd r0, r1, \[r0\]
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++** bx lr
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++*/
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++long long f1 (char *p, int i)
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++{
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++ return __atomic_load_n ((long long *)(p + i), __ATOMIC_RELAXED);
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++}
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++
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Khem Raj