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@@ -32,6 +32,10 @@ Date: Thu Jun 20 10:22:01 2024 +0100
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Upstream-Status: Backport [https://github.com/llvm/llvm-project/commit/78ff617d3f573fb3a9b2fef180fa0fd43d5584ea]
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CVE: CVE-2024-0151
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Signed-off-by: Deepesh Varatharajan <Deepesh.Varatharajan@windriver.com>
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+
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+Added back RegVT variable, which was accidentally removed during backporting.
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+
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+Signed-off-by: Gyorgy Sarvari <skandigraun@gmail.com>
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---
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diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
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index 900113244e41..e12f8c183db2 100644
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@@ -98,16 +102,15 @@ index 900113244e41..e12f8c183db2 100644
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Function::const_arg_iterator CurOrigArg = MF.getFunction().arg_begin();
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unsigned CurArgIdx = 0;
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-@@ -4432,7 +4450,7 @@ SDValue ARMTargetLowering::LowerFormalArguments(
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- }
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+@@ -4433,6 +4451,7 @@ SDValue ARMTargetLowering::LowerFormalArguments(
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// Arguments stored in registers.
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if (VA.isRegLoc()) {
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-- EVT RegVT = VA.getLocVT();
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+ EVT RegVT = VA.getLocVT();
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+ SDValue ArgValue;
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if (VA.needsCustom() && VA.getLocVT() == MVT::v2f64) {
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// f64 and vector types are split up into multiple registers or
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-@@ -4496,16 +4514,6 @@ SDValue ARMTargetLowering::LowerFormalArguments(
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+@@ -4496,16 +4515,6 @@ SDValue ARMTargetLowering::LowerFormalArguments(
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case CCValAssign::BCvt:
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ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
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break;
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@@ -124,7 +127,7 @@ index 900113244e41..e12f8c183db2 100644
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}
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// f16 arguments have their size extended to 4 bytes and passed as if they
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-@@ -4515,6 +4523,15 @@ SDValue ARMTargetLowering::LowerFormalArguments(
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+@@ -4515,6 +4524,15 @@ SDValue ARMTargetLowering::LowerFormalArguments(
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(VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16))
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ArgValue = MoveToHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), ArgValue);
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